Professor S.R. Maeng
Course Description
This course is an introduction to modern digital systems. We will examine the fundamental concepts of digital systems at all levels, also covering the practical aspects of modern system design: hardware description languages (VHDL) which are widely used in industry. Students will gain hands-on experience in designing and implementing a number of real digital systems using CAD tools and FPGAs.
Topics:
Boolean Algebra; CAD tools; VHDL; Implementation Technology;
Optimization of Logic Functions; Number Representation; MUXs;
Decodes; F/F. registers, counters; Synchronous Sequential Circuit
design; several design examples;
Course Grading
Labs: 30%
Exams (2) : 20 % each
Homework and Reading assingments: 30 %
* Sharing or copying of solutions is not allowed. Of course, cooperation on exams is not allowed.
Course Texts
Required;
Brown & Vranesic, Fundamentals of digital logic with VHDL design,
3rd ed, McGraw Hill, 2009.
Handouts for Lab.
Optional;
R. H. Katz, Contemporary Logic Design, Benjamin/Cummings
Instructor
Professor : Seungryoul
Maeng
Office: Room 4403
E-mail: maeng@kaist.ac.kr
Phone: 3519
Lecture Hours: Mon 11:00 - 12:15, Wed 11:00 - 12:15
Office Hours:
Mon 13:00 - 14:00, Wed 13:00 - 14:00
Lab Schedule: TBD
TAs: Hyotaek Shim, Jinho Seol, Bonkeun Seo, Youngjin Kwon
BBS
A BBS has been set up for this course. Click here to enter the BBS.
LAB Outline: (Tentative)
| 1 | VHDL, Quartus Simulation |
| 2 | Switch, LED, 7-seg Control Program |
| 3 | BCD add/sub Circuit Design |
| 4 | Multiplier, lpm_mult Design and Implementation |
| 5 | Register, Counter Design and Implementation |
| 6 | 3-digit BCD Counter Implementation |
| 7 |
Latch, Flip-flop, Counter Implementation |
| 8 |
FSM Design and Implementation |
| 9 | RAM implementation using LPM |
Lecture Notes
* This schedule is subject to change.*
| Topic | Reading Assignments | Homework | Remarks | |
| 2/2 | Course Overview and Design concepts |
RA#1: Read Section 2.1-2.7 in the text book. Submit a summary report. (Due Monday 2/9) |
||
| 2/4 | No class on Wed 2/4 | |||
| 2/9, 2/11 | Introduction Logic Functions Truth table Boolean Algebra Synthesis Using NAND and NOR networks Design Examples |
RA#2: Read Section 3.1-3.7, 3.9 in the text book. Submit a summary report. (Due Wed 2/18, noon) |
|
|
| 2/16 | Introduction to VHDL | HW#1 (Due Mon, Feb 23) | ||
| 2/18 | Introduction to CAD Tool |
RA#3: Read Section 4.1-4.10. Submit a summary report. (Due Mon, Mar 2) |
||
| 2/23, 25 |
Implementation Technology |
RA#4: Read Section 5.1-5.4, 5.7. Submit a summary report. (Due Mon, Mar 9) |
||
| 3/2 | Implementation Technology |
|
HW#2 (Due Mon, Mar 16) | |
| 3/4 | Optimized Implementation of Logic
Functions Karnaugh Map |
RA#5: Read Section 6.1- 6.5. Submit a summary report.(Due Tue, Mar 17) |
||
| 3/9 | Multilevel synthesis | |||
| 3/11, 3/16 | Number Representation and Arithmetic
Circuits Positional Number System Signed Numbers Arithmetic Circuits |
Read Section 7.1- 7.11, 7.14-15 Submit a summary report.(Due Mon, Mar 30) |
|
|
| 3/18 | Combinational circuit Building Blocks
MUX, DEMUX, Encoder Arithmetic comparison |
|||
| 3/25 | Midterm Exam | 11:00-12:30 | ||
| 3/30, 4/1,4/6-8 | FLIP-FLOPS, Registers, Counters |
Read Section 8.1- 8.3, 8.6-8.7 Submit a summary report.(Due Wed, April 8) |
|
|
| 4/13 | Design Examples |
RA#8: Read Section 9.1-9.2, 9.6. Submit a summary report.(Due Wed, April 22) |
HW#3 (Due Mon, Apr 20) | |
| 4/15, 4/20 | Synchronous Sequential Circuits Basic design steps |
|||
| 4/22, 4/27 |
HW#4(Due Mon, May 11) |
|
||
| 4/29. 5/4,5/6 | Asynchronous sequential circuits Hazards, design examples |
HW#5(Due Mon, May 18) | ||
| 5/11, 5/13 | Study week (no classes) |
|
||
|
5/20 |
Final Exam | 11:00-13:00 |
<Previous Examinations>
2006 Midterm Exam
2006 Final Exam
2007 Midterm Exam
2007 Final Exam